1) Field of the Invention
This invention relates generally to fabrication of a threshold voltage adjustment layer for a semiconductor device and more particularly to an oblique implant process to form an improved threshold voltage adjustment layer to improve the reverse narrow width effect for the fabrication of a CMOS semiconductor device.
2) Description of the Prior Art
In the forming of large scale integrated circuits using field effect transistors, reducing the leakage current and increasing the threshold voltages near the bird's beak in field oxide regions is of critical importance.
In a conventional process, as shown in FIG. 1, a field oxide region 102 is formed on a substrate. A vertical boron implant (B or BF.sub.2) is performed to form a channel stop layer and also a punchthru stop 106. We have noted that a problem with this structure is the peak concentration of the ptype implant is far from the interface of the field oxide and the silicon near the bird's beak area 108. This structure suffers from a "reverse narrow width effect" where the threshold voltage is reduced and the leakage current is increased as the width of the device is scaled.
Furthermore, as devices are shrunk further and various LOCOS and non-LOCOS isolation techniques are implemented, the sharp transition between the field oxide and the gate oxide at the edges of the device causes a penetration of the electric field from the active channel to field regions. This increases the threshold voltage of the device. However, when the channel stop implant/punchthru stop implant is performed after field oxidation, the depletion of surface concentration results in a lower threshold voltage as the width of channel decreases. This is called reverse narrow width effect.
Therefore, an improved method should be developed to reduce this reverse narrow width problem. Workers in the field have attempted to solve other semiconductor isolation problems. U.S. Pat. No. 5,518,941 (Lin et al.) shows a method of forming field implant channel stop regions and a device using a field implant channel stop region to improve isolation between devices in integrated circuits using field effect transistors. The field implant channel stop region is formed by a large angle titled implant beam or a higher energy normally directed implant.
U.S. Pat. No. 5,344,787 (Nagalingam et al.) shows a method of forming P-channel connected to N.sup.+ S/D regions formed using an angled implant. U.S. Pat. No. 5,396,096 (Akamatsu et al.) shows a method of forming a channel stop region under the isolation.